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DM74LS469 8-Bit Up/Down Counter
April 1998
DM74LS469 8-Bit Up/Down Counter
General Description
The 'LS469 is an 8-bit synchronous up/down counter with parallel load and hold capability. Three function-select inputs (LD, UD, CBI) provide one of four operations which occur synchronously on the rising edge of the clock (CK). The LOAD operation loads the inputs (D7-D0) into the output register (Q7-Q0). The HOLD operation holds the previous value regardless of clock transitions. The INCREMENT operation adds one to the output register when the carry-in input is TRUE (CBI = LOW), otherwise the operation is a HOLD. The carry-out (CBO) is TRUE (CBO = LOW) when the output register (Q7-Q0) is all HIGHs, otherwise FALSE (CBO = HIGH). The DECREMENT operation subtracts one from the output register when the borrow-in input is TRUE (CBI = LOW), otherwise the operation is a HOLD. The borrow-out (CBO) is TRUE (CBO = LOW) when the output register (Q7-Q0) is all LOWs, otherwise FALSE (CBO = HIGH). The output register (Q7-Q0) is enabled when OE is LOW, and disabled (HI-Z) when OE is HIGH. The output drivers will sink the 24 mA required for many bus-interface standards. Two or more 'LS469 octal up/down counters may be cascaded to provide larger counters.
Features/Benefits
n 8-bit up/down counter for microprogram-counter, DMA controller and general-purpose counting applications n 8 bits matches byte boundaries n Bus-structured pinout n 24-pin SKINNYDIP saves space n 3-STATE outputs drive bus lines n Low current PNP inputs reduce loading n Expandable in 8-bit increments
Connection Diagram
Top View
Standard Test Load
DS008333-3
DS008333-1
Order Number DM54LS469J, DM74LS469J or DM74LS469N See Package Number J24F or N24C
(c) 1998 Fairchild Semiconductor Corporation
DS008333
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Function Table
OE H L L L L L CK X

LD X L H H H H
UD X X L L H H
CBI X X H L H L
D7-D0 X D X X X X
Q7-Q0 Z D Q Q plus 1 Q Q minus 1
Operation HI-Z LOAD HOLD INCREMENT HOLD DECREMENT
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Absolute Maximum Ratings (Note 1)
Supply Voltage VCC Input Voltage 7V 5.5V
Off-State Output Voltage Storage Temperature
5.5V -65C to +150C
Operating Conditions
Symbol VCC TA tW tSU th Supply Voltage Operating Free-Air Temperature Width of Clock Set Up Time Hold Time Low High Parameter Min 4.5 -55 40 30 60 0 -15 Military Typ 5 Max 5.5 125 (Note 2) Min 4.75 0 35 25 50 0 -15 ns 10 Commercial Typ 5 Max 5.25 75 V C ns Units
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. Note 2: Case Temperature
Electrical Characteristics
Over Operating Conditions Symbol VIL VIH VIC IIL IIH II VOL Parameter Low-Level Input Voltage High-Level Input Voltage Input Clamp Voltage Low-Level Input Current High-Level Input Current Maximum Input Current Low-Level Output Voltage VCC = MIN VCC = MAX VCC = MAX VCC = MAX VCC = MIN VIL = 0.8V VIH = 2V VCC = MIN VOH IOZL Off-State Output Current IOZH IOS ICC Output Short-Circuit Current (Note 3) Supply Current High-Level Output Voltage VIL = 0.8V VIH = 2V VCC = MAX VIL = 0.8V VIH = 2V VCC = 5.0V VCC = MAX II = -18 mA VI = 0.4V VI = 2.4V VI = 5.5V MIL COM MIL COM IOL = 12 mA 0.5 IOL = 24 mA IOH = -2 mA 2.4 IOH = -3.2 mA VO = 0.4V VO = 2.4V VO = 0V -100 100 -30 120 -130 180 V A A mA mA V 2 -1.5 -0.25 25 1 Test Conditions Min Typ (Note 4) Max 0.8 Units V V V mA A mA
Note 3: No more than one output should be shorted at a time and duration of the short-circuit should not exceed one second Note 4: All typical values are VCC = 5V, TA = 25C.
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Switching Characteristics
Over Operating Conditions Symbol fMAX tPD tPD tPD tPZX tPXZ Parameter Maximum Clock Frequency CBI to CBO Delay Clock to Q Clock to CBO Output Enable Delay Output Disable Delay CL = 50 pF R1 = 200 R2 = 390 Test Conditions (See Test Load/Waveforms) Min 10.5 35 20 55 20 20 60 35 95 45 45 Military Typ Max Commercial Min 12.5 35 20 55 20 20 50 30 80 35 35 Typ Max MHz ns ns ns ns ns Units
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Logic Diagram
LS469
DS008333-2
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Physical Dimensions
inches (millimeters) unless otherwise noted
24-Pin Narrow Ceramic Dual-In-Line Package (J) Order Number DM54LS469J or DM74LS469J Package Number J24F
24-Pin Narrow Plastic Dual-In-Line Package (N) Order Number DM74LS469N Package Number N24C
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DM74LS469 8-Bit Up/Down Counter
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and (c) whose device or system, or to affect its safety or effectiveness. failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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